1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dynamic clock signal generating circuit for use in a synchronous Dynamic Random Access Memory (DRAM) device.
2. Description of the Related Art
Typically, DRAM devices are asynchronously controlled by a control device such as a microprocessor. The microprocessor provides an address to DRAM input terminals and strobes the address by using row and column address strobe signals. The address is held valid for a required minimum time. During the time the address is held valid, the DRAM device accesses the addressed cells. Thereafter, the DRAM writes new data from the microprocessor to selected memory cells or provides the data from selected memory cells to its output terminal for the microprocessor to read the data. The processor is in a standby state while the DRAM performs various internal operations, such as precharge, address decoding, data sensing, data output through an output buffer, and the like. Because the microprocessor is essentially idle during the standby state, the system operating speed is adversely affected. DRAM devices which free up the microprocessor to perform other tasks during the standby period and speed up the input and output of data have been recently developed.
Synchronous DRAM typically includes a clock signal buffer for converting a system clock signal typically supplied by the processor into a level suitable for internal circuitry. By utilizing the clock signal buffer, each circuit within the memory device operates responsive to the system clock signal. However, since the clock signal buffer generates the internal clock signal by buffering the externally supplied system clock signal, a time delay between the external system clock signal and the internal clock signal is inevitably generated due to the delay of the buffer. If the external and internal clock signals are skewed, the internal operation of the device when the external clock signal is supplied is delayed. Accordingly, a need exists for a clock signal generating circuit which generates an internal clock signal with a minimized delay with respect to the external system clock signal.